1. Field of the Invention
The present invention relates to a measurement apparatus that carries out a performance measurement of a PLL (Phase-Locked Loop) circuit and a method therefor. The present invention also relates to a reproduction apparatus including a structure of the measurement apparatus, that reproduces data from a recording medium.
2. Description of the Related Art
PLL circuits are generally provided to communication apparatuses such as a modem and apparatuses that execute data decoding processing in a signal reproduction process in addition to storage apparatuses that perform recording and reproduction in accordance with recording media such as an optical disc recording medium, a magnetic disk recording medium, and a tape-like recording medium. For carrying out appropriate data decoding processing, the PLL circuit needs to be in a locked state and a reproduction signal having a synchronized phase needs to be input to a data decoding processing system.
For example, although an error rate can be used as an evaluation criterion in evaluating performance and quality of the storage apparatuses and recording media described above, a more-accurate evaluation result can be obtained if a judgment on whether the PLL circuit is locked is made in advance. If a state where the PLL circuit is locked and converged is judged in advance, an error rate due to causes other than the PLL circuit can be judged appropriately. Based on this point, a technique that enables operation performance of the PLL circuit to be measured and a convergence state of the PLL circuit to be judged is of a great significance.
For example, “A Parallel Architecture of Interpolated Timing Recovery for High-Speed Data Transfer Rate and Wide Capture-Range” by HIGASHINO Satoru, KOBAYASHI Shoei, and YAMAGAMI Tamotsu, Technical Digest of Optical Data Storage (ODS) 2007, TuB5, describes a technique of directly observing a phase error detected by a PLL circuit in measuring performance of the PLL circuit.